? semiconductor components industries, llc, 2005 september, 2005 ? rev. 1 1 publication order number: NTMFS4120N/d NTMFS4120N power mosfet 30 v, 31 a, single n?channel, so?8 flat lead features ? low r ds(on) ? optimized gate charge ? low inductance so?8 package ? these are pb?free devices* applications ? notebooks, graphics cards ? dc?dc converters ? synchronous rectification maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain?to?source v oltage v dss 30 v gate?to?source v oltage v gs 20 v continuous drain current (note 1 ) steady state t a = 25 c i d 18 a t a = 85 c 13 t 10 s t a = 25 c 31 power dissipation (note 1 ) steady state t a = 25 c p d 2.2 w t 10 s 6.9 continuous drain current (note 2) steady state t a = 25 c i d 11 a t a = 85 c 8.0 power dissipation (note 2) t a = 25 c p d 0.9 w pulsed drain current t p = 10 s i dm 94 a operating junction and storage temperature t j , t stg ?55 to 150 c source current (body diode) i s 7.0 a single pulse drain?to?source avalanche energy (v dd = 30 v, v gs = 10 v, i pk = 30 a, l = 1 mh, r g = 25 ) e as 450 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c thermal resistance maximum ratings parameter symbol value unit junction?to?ambient ? steady state (note 1) r ja 55.8 c/w junction?to?ambient ? t 10 s (note 1) r ja 18 junction?to?ambient ? steady state (note 2) r ja 139.1 maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. surface mounted on fr4 board using 1 in sq pad size (cu area = 1.127 in sq [1 oz] including traces). 2. surface mounted on fr4 board using the minimum recommended pad size (cu area = 1.0 in sq). g d s device package shipping ? ordering information NTMFS4120Nt1g so?8 fl (pb?free) 1500 tape & ree l so?8 flat lead case 488aa style 1 4120n = specific device code a = assembly location y = year ww = work week = pb?free package (note: microdot may be in either location) 1 marking diagram 4120n ayww s s s g d d d d ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. http://onsemi.com NTMFS4120Nt3g so?8 fl (pb?free) 5000 tape & ree l 30 v 4.2 m @ 4.5 v 3.5 m @ 10 v r ds(on) typ 31 a i d max (note 1) v (br)dss *for additional information on our pb?free strateg y and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
NTMFS4120N http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol test condition min typ max unit off characteristics drain?to?source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 30 v drain?to?source breakdown voltage temperature coefficient v (br)dss /t j 21 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 24 v t j = 25 c 1.0 a t j = 125 c 10 gate?to?source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 3) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.0 2.5 v negative threshold temperature coefficient v gs(th) /t j 7.4 mv/ c drain?to?source on resistance r ds(on) v gs = 10 v, i d = 26 a 3.5 4.5 m v gs = 4.5 v, i d = 24 a 4.2 5.5 forward transconductance g fs v ds = 15 v, i d = 26 a 35 s charges, capacitances and gate resistance input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 24 v 3600 pf output capacitance c oss 640 reverse transfer capacitance c rss 380 total gate charge q g(tot) v gs = 4.5 v, v ds = 15 v, i d = 24 a 33 50 nc threshold gate charge q g(th) 4.4 gate?to?source charge q gs 13 gate?to?drain charge q gd 14 gate resistance r g 1.0 switching characteristics (note 4) turn?on delay time t d(on) v gs = 4.5 v, v ds = 15 v, i d = 1.0 a, r g = 3.0 24 ns rise time t r 32 turn?off delay time t d(off) 27 fall time t f 31 drain?source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 6.0 a t j = 25 c 0.74 1.0 v t j = 125 c 0.6 reverse recovery time t rr v gs = 0 v, di s /dt = 100 a/ s, i s = 6.0 a 36 ns charge time t a 18 discharge time t b 18 reverse recovery charge q rr 34 nc 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
NTMFS4120N http://onsemi.com 3 typical performance curves t j = 125 c 0 20 2 v ds , drain?to?source voltage (volts) i d, drain current (amps) 10 0 figure 1. on?region characteristics 3 30 20 0 figure 2. transfer characteristics v gs , gate?to?source voltage (volts) figure 3. on?resistance vs. drain current and temperature r ds(on), drain?to?source resistance ( ) i d, drain current (amps) figure 4. on?resistance vs. drain current and gate voltage i d, drain current (amps) ?50 0 ?25 25 1.4 1.6 1 0.8 0.6 50 150 figure 5. on?resistance variation with temperature t j , junction temperature ( c) t j = 25 c t j = ?55 c 75 t j = 25 c i d = 26 a v gs = 10 v r ds(on), drain?to?source resistance (normalized) t j = 25 c r ds(on), drain?to?source resistance ( ) v gs = 10 v 100 figure 6. drain?to?source leakage current vs. voltage v ds , drain?to?source voltage (volts) 20 v gs = 0 v i dss , leakage (na) t j = 150 c t j = 125 c 3.0 v 3.2 v v gs = 4.5 v v ds 10 v 10 25 2.8 v 10 4 3 0 80 30 v gs = 3.8 v to 10 v 40 80 125 100 5 20 80 0.006 i d, drain current (amps) 0.001 t j = 25 c v gs = 10 v 0.003 0.004 0.007 10 40 50 0.008 t j = 125 c t j = ?55 c 30 0.006 0.003 0.007 0.002 0.004 0.005 1000 5 50 410 50 12 20 8 0 10 40 50 30 1.2 15 40 68 10000 3.4 v 3.6 v 0.005 70 60 70 60 60 70 70 60 0.002
NTMFS4120N http://onsemi.com 4 typical performance curves figure 7. capacitance variation figure 8. gate?to?source and drain?to?source voltage vs. total charge 1.0 5 0 v sd , source?to?drain voltage (volts) figure 9. resistive switching time variation vs. gate resistance i s , source current (amps) v gs = 0 v t j = 25 c 45 25 figure 10. diode forward voltage vs. current 0.8 0.6 20 15 figure 11. maximum rated forward biased safe operating area 0.1 v ds , drain?to?source voltage (volts) 0.1 1 i d , drain current (amps) r ds(on) limit thermal limit package limit v gs = 20 v single pulse t c = 25 c 10 0.01 dc 1 100 10 10 ms 1 ms 100 s gate?to?source or drain?to?source voltage (volts) r g , gate resistance (ohms) 1 10 100 100 10 t, time (ns) v dd = 15 v i d = 1 a v gs = 4.5 v t d(on) 1000 t f t d(off) 10 1000 10 s 30 150 50 0 t j , junction temperature ( c) i d = 30 a 500 250 figure 12. maximum avalanche energy vs starting junction temperature 75 50 200 150 100 25 300 eas, single pulse drain?to?source avalanche energy (mj) 100 125 v gs , gate?to?source voltage (volts) 0 3 0 q g , total gate charge (nc) 5 4 51015 v dd = 15 v v gs = 4.5 v i d = 24 a t j = 25 c v gs q gs 35 q gd qt 2 1 c, capacitance (pf) 1000 0510 c iss c oss c rss 15 20 0 2000 3000 4000 5000 6000 25 t j = 25 c 25 20 35 0.9 0.7 0.5 40 100 30 t r 350 400 450
NTMFS4120N http://onsemi.com 5 figure 13. thermal response t, time (seconds) rthja(t), effective transient thermal resistance 0.1 d = 0.5 single pulse 1e?04 1e?03 1e?02 1e?01 0.2 0.01 1e+03 0.001 1 0.02 0.05 0.1 1e+00 1e+01 1e+02 0.01
NTMFS4120N http://onsemi.com 6 package dimensions so?8 flat lead case 488aa?01 issue a style 1: pin 1. source 2. source 3. source 4. gate 5. drain 6. drain m 3.00 3.40 0 ??? 3.80 12 1234 5 6 top view d1 e1 d e 2 2 b a 0.20 c 0.20 c 2 x 2 x dim min nom millimeters a 0.90 0.99 a1 0.00 ??? b 0.33 0.41 c 0.23 0.28 d 5.15 bsc d1 4.50 4.90 d2 3.50 ??? e 6.15 bsc e1 5.50 5.80 e2 3.45 ??? e 1.27 bsc g 0.51 0.61 k 0.51 ??? l 0.51 0.61 l1 0.05 0.17 detail a a1 e 3 x c 4 x c seating plane max 1.20 0.05 0.51 0.33 5.10 4.22 6.10 4.30 0.71 ??? 0.71 0.20 side view bottom view a 0.10 c 0.10 c detail a 14 6 l1 e/2 8x d2 g e2 k b a 0.10 b c 0.05 c l 5 m notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. dimension d1 and e1 do not include mold flash protrusions or gate burrs. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, r epresentation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 NTMFS4120N/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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